This invention relates to a semiconductor device and, more particularly to a semiconductor device calling for of high-speed operation.
Recently, semiconductor integrated memory devices with MOS transistors have remarkably developed. As objectives to be attained in the future, there are large-scale integration and speed-up in operation. Speed-up in operation of the MOS memory may be realized by reducing data readout time tACC. As is generally known, the operating speed of a MOS integrated circuit may substantially be affected by charge and discharge times of capacitances parasitic on the circuit. Therefore, reduction in the stray capacitance of the circuit will lead to an increase in the operating speed.
In the case of the MOS integrated circuit, the stray capacitances may generally include a gate capacitance provided by an insulating film under a gate electrode and a diffusion capacitance or junction capacitance by a PN junction which is reverse-biased. It is well known that the diffusion capacitance is in inverse proportion to the square root of the reverse bias voltage of the PN junction. Accordingly, the diffusion capacitance may be reduced by increasing the reverse bias voltage applied to the substrates of the MOS transistors or wells.
In a CMOS memory device, each memory cell stores data statically when the memory is quiescent (when the memory device is not used). At time of operation, the peripheral circuits operate to read out data from an accessed memory cell. Therefore, it is effective to increase the operating speed of the peripheral circuits for reduction of the data readout time tACC. That is, it is desired that the junction capacitance at the peripheral circuits be reduced.
In the MOS integrated circuit, there are generally used two operating potentials V.sub.DD (e.g.,+5 V) and V.sub.SS (GND). It is possible externally to supply a reverse bias potential capable of reducing the capacitance of the PN junctions in the peripheral circuits, which may not, however, be advantageous to the integrated circuit. Thus, the reverse bias potential to reduce the junction capacity should preferably be produced inside the integrated circuit.
Moreover, according to an approach to shorten the operating time by reducing only the junction capacitance of the peripheral circuits instead of uniformly reducing the junction capacitances of the memory cell array and the peripheral circuits, the reverse bias potential to reduce the junction capacitance of the peripheral circuits may be supplied only at time of operation. In applying the capacitance-reducing reverse bias potential to the memory cell array at operation, the substrate potential of MOS transistors in a memory cell varies from an operating time to a non-operating time, varying the threshold voltage of the MOS transistors and causing stored data to be lost.
In a CMOS integrated circuit, MOS transistors of one channel type are formed in wells of one conductivity type with an impurity concentration higher than that of a semiconductor substrate of the other conductivity type, while MOS transistors of the other channel type are formed in the substrate. Accordingly, the junction capacitance of the MOS transistors formed in the wells is larger than that of the MOS transistors formed in the semiconductor substrate, so that reduction in capacitance of the MOS transistors in the wells will contribute to the speed-up in operation.